1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a sense amplifier select circuit for use in a memory device consisting of cell arrays and sense amplifier arrays arranged in a shared sense amplifier mode, and method of selecting the same.
2. Discussion of Related Art
Generally, as the area of a cell becomes small, it becomes impossible to draw one bit line sense amplifier (BLSA) within a width of one cell. Therefore, a shared sense amplifier in which one bit line sense amplifier is drawn into two cell regions and the bit line sense amplifier is shared by neighboring upper and lower memory cell arrays, has been widely used. This shared sense amplifier mode can reduce a total chip area.
A sense amplifier connecting structure of a shared sense amplifier mode according to a prior art will now be described with reference to FIG. 1.
When a cell array (2) is driven, a bit line sense amplifier array (2) and a bit line sense amplifier (BLSA) array (3) are together driven to amplify all the cells of the cell array (2), so that they can be sensed. Accordingly, if the cell array (2) is selected, a cell array (1) and a cell array (3) are not selected. A bit line sense amplifier array (2) precludes a portion connected to the cell array (1) and the bit line sense amplifier array (3) precludes a portion connected to the cell array (3). For instance, if the cell array (2) is selected, signals (BISL2, BISL3) outputted from a sense amplifier select circuit (or bit line isolation circuit: now shown) become a logical Low and signals (BISH2, BISH3) outputted therefrom become a logical High. As a result, the cell array (2) is connected to the bit line sense amplifier arrays (2), (3).
FIG. 2 is a partially expanded view of the sense amplifier structure of the shared sense amplifier mode shown in FIG. 1. In FIG. 2, only one cell and one bit line sense amplifier are shown in the cell array (2) and the bit line sense amplifier array (3). NMOS transistors N1, N2: 10 each having a gate to which a BISH signal is applied serve as a switch for connection to a cell on an upper side. NMOS transistors N10, N11: 40 to which BISL signals are applied serve as a switch for connection to a cell on a lower side.
Meanwhile, PMOS transistors P1, P2 for pulling up a bit line BL to a logical High and NMOS transistors N3, N4 for pulling down the bit line BL to a logical Low constitutes a sense amplifier 20. The structure further includes a bit line equalization circuit 30 having NMOS transistors N7, N8 and N9 for initializing the bit line BL and each node of the bit line sense amplifier BLSA by means of a bit line precharge signal (BLP), and NMOS transistors N5, N6 for transmitting data of the bit line BL to a line LDB in accordance with application of a column address (YI).
In such a structure, the bit line sense amplifier array 2 determines which of cell arrays 2 and 3 will be used based on a logical state of the BISH and BISL signals. If the cell array 2 is selected, the BISH signal becomes a logical High. Therefore, the NMOS transistors N1, N2 are turned on and data of the cell array 2 are transferred to the sense amplifier, so that they can be sensed. At this time, in the cell array 3 not selected, the BISL signal becomes a logical Low. The NMOS transistors N10, N11 are turned off and a path to the cell array 3 is thus precluded.
Meanwhile, in case where a memory such as a DRAM cell, etc. is employed, the memory has to be refreshed on a regular basis in order to keep cell data. To this end, the refresh operation is usually performed by means of an address counter, while increasing an internal address. A refresh operation that is generally performed in a shared sense amplifier mode shown in FIG. 2 will be described with reference to FIG. 3. As described above, a case where the cell array 2 and the bit line sense amplifier array 3 are connected will be described.
Referring to FIG. 3, in order to electrically connect the cell array 2 and the bit line sense amplifier array 3, a BISH signal of a logical High is applied to turn on the NMOS transistors N1, N2 and a BISL signal of a logical Low is applied to turn off the NMOS transistors N10, N11. Thereafter, after the bit line precharge (BLP) signal that initializes the bit line BL and a bit line_bar BLB is disabled to enable a word line WL, if the bit line sense amplifier BLSA is enabled, data of the cell node CN is shared. Its signal is amplified by the bit line sense amplifier BLSA and is then restored to the cell node CN. Thereby, the refresh operation is completed.
FIG. 4 is a diagram showing the configuration of a sense amplifier select circuit according to a prior art and FIG. 5 is a waveform showing the operation of the sense amplifier select circuit according to a prior art.
Referring to FIG. 4, in a conventional sense amplifier select circuit 100, if a block select signal (Block Selection Bar: bsb) of a logical Low instead of a logical High is applied and a corresponding block is thus selected, the output of an inverter INV2 becomes a logical High. This High-level signal enables a NMOS transistor N1 to be turned on. The transistor N1 then enables a PMOS transistor P1 to be turned on, which allows a node pcg to be a logical High. Accordingly, a PMOS transistor P2 is turned off and a node iso keeps a logical Low. If the node iso keeps a logical Low, the signal (bis) that is amplified through inverters INV3, INV4 also keeps a logical Low. In this case, the node pcg keeps a logical High since the NMOS transistor N4 is turned off.
Thereafter, if an enable signal (sgdb) of the sense amplifier becomes a logical Low, the sense amplifier is at an enable state. If the enable signal (sgdb) becomes a logical High again, the sense amplifier finishes its sensing operation. At this time, the node pcg keeps a logical Low. In this case, if a logical High signal is applied to the node iso, the signal (bis) is outputted as a logical High through the inverters INV3, INV4. A NMOS transistor N5 serves as a latch. If an input does not have a specific function, the NMOS transistor N5 functions to keep the signal (bis) Low.
As described above, according to a prior art, as an address is continuously increased within one block due to the use of an internal counter upon a refresh operation, a refresh operation is continuously executed while a bit line is changed under a condition that the same cell array is selected. Accordingly, under this condition, as a cell voltage through one bit line is refreshed, a signal (BISH) must keep a logical High, while a signal (BISL) must continuously toggle a logical High and a logical Low. In other words, the NMOS transistors N10, N11 in FIG. 2 continuously toggle ON/OFF states. Due to this, there occurs a problem that unnecessary current is consumed.
In particular, in a pseudo SDRAM that performs a refresh operation on a regular basis once it enters a standby mode, standby current is increased. This poses a further serious problem.